初稿截稿日期：2019-04-08

初稿录用通知日期：2019-06-21

摘要截稿日期：2019-04-01

摘要录用通知日期：2019-06-21

终稿截稿日期：2019-07-26

Paper submissions must be made through the online submission system at the ICCAD website

Regular papers will be reviewed as finished papers; preliminary submissions will be at a disadvantage.

Authors are asked to submit their work in two stages. In stage one (abstract submission), a title, abstract, and a list of all co-authors must be submitted via the ICCAD web submission site. In stage two (paper submission), the paper itself is submitted. Authors are responsible for ensuring that their paper submission meets all guidelines, and that the PDF is readable.

• System-level specification, modeling, and simulation
• System design flows and methods
• HW/SW co-design, co-simulation, co-optimization, and co-exploration
• HW/SW platforms for rapid prototyping
• System design case studies and applications
• System-level issues for 3D integration
• Micro-architectural transformation
• Memory architecture and system synthesis
• System communication architecture
• Network-on-chip design methodologies and CAD
• Modeling and simulation of heterogeneous platforms
• High-level synthesis for heterogeneous computing
• Power/performance analysis of heterogeneous and cloud platforms
• Programming environment of heterogeneous computing
• Application driven heterogeneous platforms for big data, machine learning etc.
• Applications and designs for systems based on optical devices

• Multi-core/multi-processors systems
• HW/SW co-design for embedded systems
• Static and dynamic reconfigurable architectures
• Memory hierarchies and management
• System-level consideration of custom memory/storage architectures
• Application-specific instruction-set processors (ASIPs)
• CAD for Internet-of-Things (IoT) and sensor networks
• Design issues for Internet-of-Things (IoT) Devices
• Modeling and analysis of CPS
• CAD for automotive systems and power electronics
• Dependable and safe CPS design
• Analysis and optimization of data centers
• CAD for display electronics
• Green computing (smart grid, energy, solar panels, etc.)

• Hardware and devices for neuromorphic and neural network computing
• Design method for learning on a chip
• Systems for neural computing (including deep neural networks)
• Neural network acceleration techniques including GPGPU, FPGA and dedicated
• ASICs
• CAD for bio-inspired and neuromorphic systems

• Real-time software and operating systems
• Middleware and virtual machines, runtime support and resource management
• Timing analysis and WCET
• Profiling and compilation techniques, domain-specific embedded libraries
• Design exploration, synthesis, validation, verification, and optimization
• Software techniques and programming models for multicores, GPUs, and multithreaded embedded architectures
• System and embedded software security techniques
• Malware and Cloud security
• Security and privacy for the Internet of Things
• Embedded software forensics

• Hardware-based security (CAD for PUF’s, RNG, AES etc)
• Detection and prevention of hardware Trojans
• Side-channel attacks, fault attacks and countermeasures
• Split Manufacturing for security
• Design and CAD for security
• Security implications of CAD
• Cyberphysical system security
• Nanoelectronic security
• Supply chain security and anti-counterfeiting

• Power and thermal estimation, analysis, optimization, and management techniques for hardware and software systems
• Energy- and thermal aware application mapping and scheduling
• Energy- and thermal-aware dark silicon system design and optimization
• Energy- and thermal-aware architectures, algorithms and techniques
• Run-time management for the dark silicon
• New hardware techniques for approximate/stochastic computing

• High-level/Behavioral/Logic synthesis
• Technology-independent optimization and technology mapping
• Functional and logic timing ECO
• Resource scheduling, allocation, and synthesis
• Interaction between logic synthesis and physical design

• High-level/Behavioral/Logic modeling and validation
• High-level/Behavioral/Logic simulation
• Formal, semi-formal, and assertion-based verification
• Equivalence and property checking
• Emulation and hardware simulation/acceleration
• Post-silicon functional validation
• Digital fault modeling and simulation
• Delay, current-based, low-power test
• ATPG, BIST, DFT, and compression
• Memory test and repair
• Core, board, system, and 3D IC test
• Post-silicon validation and debug
• Analog, mixed-signal, and RF test

• Cell-library design and optimization
• Transistor and gate sizing
• High-level physical design and synthesis
• Estimation and hierarchy management
• 2D and 3D partitioning, floorplanning, and placement
• Post-placement optimization
• Buffer insertion and interconnect planning

• 2D and 3D clock network synthesis
• 2D and 3D global and detailed routing
• Package-/Board-level routing and chip-package-board co-design
• Post-layout/-silicon optimization
• Layout and routing issues for optical interconnects

• Process technology characterization, extraction, and modeling
• CAD for design/manufacturing interfaces
• CAD for reticle enhancement and lithography-related design
• Variability analysis and statistical design and optimization
• Yield estimation and design for yield
• Physical verification and design rule checking
• DFM for emerging devices (3D, nanophotonics, non-volatile logic/memory, etc.)
• Machine learning for smart manufacturing and process control
• Analysis and optimization for device-level reliability issues (stress, aging effects,
• ESD, etc.)
• Analysis optimization for interconnect reliability issues (electromigration, thermal,
• etc.)
• Reliability issues related to soft errors
• Design for resilience and robustness
• Reliability issues for emerging devices (3D, optical, non-volatile, etc.)

• Deterministic and statistical static timing analysis and optimization
• Power and leakage analysis and optimization
• Circuit and interconnect-level low power design issues
• Power/ground network analysis and synthesis
• Signal integrity analysis and optimization

• CAD for analog, mixed-signal, RF
• CAD for mixed-domain (semiconductor, nanoelectronic, MEMS, and electrooptical) devices, circuits, and systems
• CAD for nanophotonics and optical devices
• Analog, mixed-signal, and RF noise modeling and simulation
• Device, interconnect and circuit extraction and simulation
• Package modeling and analysis
• EM simulation and optimization
• Behavior modeling of devices and interconnect
• Modeling of complex dynamical systems (molecular dynamics, fluid dynamics, computational finance, etc.)

• CAD for biological computing systems
• CAD for systems and synthetic biology
• CAD for bio-electronic devices, bio-sensors, MEMS, and systems

• New device structures and process technologies
• New memory technologies (flash, phase change memory, STT-RAM, memristor, etc.)
• Nanotechnologies, nanowires, nanotubes, graphene, etc.
• Quantum computing
• Optical devices, computing, and communication

David Pan--Dept. of Electrical & Computer Engineering

Iris Bahar--School of EngineeringBrown University

Yuan Xie--University of California

Rolf Drechsler--University of Bremen/DFKI

Tulika Mitra--National University of SingaporeSchool of Computing

Evangeline Young--The Chinese University of Hong KongDept. of Computer Science and Engineering

Patrick Groeneveld--Cadence Design Systems, Inc.

Ulf Schlichtmann--Technical University of MunichInstitute for EDA

Takashi Sato--Graduate School of Informatics, Kyoto UniversityDept. of Computer Science

Sri Parameswaran--Univ. of New South WalesSchool of Computer Science & Engineering

Tsung-Yi Ho--National Tsing Hua UniversityDept. of Computer Science

Nannette Jordan--MP Associates, Inc.

Yuan Xie--University of California

Rolf Drechsler--University of Bremen/DFKI